The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Nov. 16, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Juergen Pille, Stuttgart, DE;

Albert Frisch, Stuttgart, DE;

Tobias Werner, Weil im Schoenbuch, DE;

Rolf Sautter, Bondorf, DE;

Dieter Wendel, Woernitz, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0676 (2013.01); H01L 29/1037 (2013.01); H01L 29/42356 (2013.01); H01L 29/7827 (2013.01);
Abstract

An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.


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