The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Sep. 26, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Barbara S. DeWitt, Essex Junction, VT (US);

Essam Mina, St. Augustine, FL (US);

B M Farid Rahman, Columbia, SC (US);

Guoan Wang, Columbia, SC (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01P 5/18 (2006.01); H01L 23/48 (2006.01); H01P 3/08 (2006.01); H01P 11/00 (2006.01); H01P 3/00 (2006.01); H01P 3/02 (2006.01); G06F 30/394 (2020.01); H01Q 1/22 (2006.01); H01Q 13/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); G06F 30/394 (2020.01); H01P 3/003 (2013.01); H01P 3/026 (2013.01); H01P 3/081 (2013.01); H01P 11/001 (2013.01); H01P 11/007 (2013.01); H01Q 1/2283 (2013.01); H01Q 13/106 (2013.01);
Abstract

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.


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