The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Apr. 24, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Samuel Sung Shik Choi, Ballston Lake, NY (US);

Hari Prasad Amanapu, Guilderland, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76808 (2013.01); H01L 21/31055 (2013.01); H01L 21/7684 (2013.01); H01L 21/76819 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76865 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 2221/1063 (2013.01);
Abstract

Embodiments of the invention are directed to a method that includes forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar. A first interconnect structure having a substantially planar interconnect structure top surface with unintended non-planar regions is formed in the dielectric region. A reinforced planarization process is applied that includes recessing the first interconnect structure top surface to a level that is below the dielectric region top surface and the unintended non-planar region, thereby removing the unintended non-planar region and forming a second interconnect structure having a second interconnect structure top surface that is substantially planar; forming a protective cap on the second interconnect structure top surface, wherein the protective cap has a sustantially planer protective cap top surface; and recessing the dielectric region top surface to a level that is substantially planar with the protective cap top surface.


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