The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2020
Filed:
Sep. 26, 2017
Synopsys, Inc., Mountain View, CA (US);
Yoon Kah Leow, Santa Clara, CA (US);
Ting-Mao Chang, Davis, CA (US);
SYNOPSYS, INC., Mountain View, CA (US);
Abstract
An improved placement and routing method for circuit simulation includes receiving setup input controls to set up an initial arrangement of two blocks (e.g., a synthesized block and an IP block), and a designation of permutable interconnections; performing permutations of permutable interconnect signals on the, e.g., design block (or any other block)-IP block arrangement to determine an optimal permutation; compiling a bitstream comprising a final placement and route of a circuit based on the optimal permutation and generating the bitstream to be loaded onto a target FPGA; and sending the final order of the permutable signals to a permutable signals control memory structure.