The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Aug. 21, 2019
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Amir Amirkhany, Sunnyvale, CA (US);

Suresh Rajan, Fremont, CA (US);

Mohammad Hekmat, Mountain View, CA (US);

Dinesh Patil, Sunnyvale, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 11/419 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 5/02 (2006.01); G06F 13/40 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 13/4068 (2013.01); G11C 5/02 (2013.01); G11C 7/10 (2013.01); G11C 7/106 (2013.01); G11C 7/1012 (2013.01); G11C 7/1021 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 11/419 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01);
Abstract

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.


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