The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Dec. 18, 2018
Applicant:
Nxp Usa, Inc., Austin, TX (US);
Inventors:
Ramanujam Srinidhi Embar, Gilbert, AZ (US);
Ibrahim Khalil, Gilbert, AZ (US);
Abdulrhman M. S. Ahmed, Gilbert, AZ (US);
Ricardo Uscola, Tempe, AZ (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/30 (2006.01); H03F 1/32 (2006.01); H03F 1/56 (2006.01); H03F 3/213 (2006.01);
U.S. Cl.
CPC ...
H03F 1/3205 (2013.01); H03F 1/565 (2013.01); H03F 3/213 (2013.01); H03F 2200/165 (2013.01); H03F 2200/222 (2013.01); H03F 2200/267 (2013.01); H03F 2200/444 (2013.01); H03F 2200/451 (2013.01);
Abstract
A radio frequency (RF) amplifier circuit includes a field effect transistor (FET) (e.g., a FET belonging to a III-V FET enhancement group), where the FET includes a gate terminal coupled to an RF input node. The circuit further includes a prematch and biasing network coupled between a bias voltage node and the RF input node. The prematch and biasing network includes a nonlinear gate current blocking device configured to block a current from flowing between the bias voltage node and the RF input node.