The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Nov. 05, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Chuan Lin, Chiayi, TW;

Chiang-Ming Chuang, Changhua, TW;

Shang-Yen Wu, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 27/11546 (2017.01); H01L 29/423 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/31055 (2013.01); H01L 21/76294 (2013.01); H01L 27/11546 (2013.01); H01L 29/41783 (2013.01); H01L 29/42328 (2013.01); H01L 29/495 (2013.01); H01L 29/6653 (2013.01); H01L 21/3212 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.


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