The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Dec. 19, 2019
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventors:
Assignee:
Nanya Technology Corporation, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0852 (2013.01); H01L 21/823437 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0657 (2013.01); H01L 29/4238 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01);
Abstract
The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.