The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Dec. 20, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seong-Jin Song, Suwon-si, KR;

Hyun-Wook Park, Hwaseong-si, KR;

Bong-Soon Lim, Seoul, KR;

Do-Bin Kim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 8/12 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 8/12 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 16/3431 (2013.01); G11C 16/3445 (2013.01);
Abstract

In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.


Find Patent Forward Citations

Loading…