The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Nov. 13, 2019
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 8/18 (2006.01); G11C 8/10 (2006.01); G11C 11/4096 (2006.01); H04L 25/03 (2006.01); G06F 13/18 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 13/18 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1036 (2013.01); G11C 7/1039 (2013.01); G11C 7/1063 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01); G11C 7/22 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H04L 25/03057 (2013.01); H04L 25/03267 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2272 (2013.01);
Abstract
Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.