The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Apr. 24, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajkishore Barik, Santa Clara, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Xiaoming Chen, Shanghai, CN;

Dhawal Srivastava, Phoenix, AZ (US);

Anbang Yao, Beijing, CN;

Kevin Nealis, San Jose, CA (US);

Eriko Nurvitadhi, Portland, OR (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Balaji Vembu, Folsom, CA (US);

Tatiana Shpeisman, Menlo Park, CA (US);

Ping T. Tang, Edison, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3001 (2013.01); G06F 9/3017 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/3895 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01);
Abstract

One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to perform one or more machine learning operations, wherein the decode unit, based on parameters of the one or more machine learning operations, is to request a scheduler to schedule the one or more machine learning operations to one of an array of programmable compute units and a fixed function compute unit.


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