The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Jul. 22, 2019
Minehide Kusayanagi, Kanagawa, JP;
Naoyuki Ueda, Kanagawa, JP;
Yuki Nakamura, Tokyo, JP;
Yukiko Abe, Kanagawa, JP;
Shinji Matsumoto, Kanagawa, JP;
Yuji Sone, Kanagawa, JP;
Ryoichi Saotome, Kanagawa, JP;
Sadanori Arae, Kanagawa, JP;
Minehide Kusayanagi, Kanagawa, JP;
Naoyuki Ueda, Kanagawa, JP;
Yuki Nakamura, Tokyo, JP;
Yukiko Abe, Kanagawa, JP;
Shinji Matsumoto, Kanagawa, JP;
Yuji Sone, Kanagawa, JP;
Ryoichi Saotome, Kanagawa, JP;
Sadanori Arae, Kanagawa, JP;
Ricoh Company, Ltd., Tokyo, JP;
Abstract
Method for producing field-effect transistor including source electrode and drain electrode, gate electrode, active layer, and gate insulating layer, the method including etching the gate insulating layer, wherein the gate insulating layer is metal oxide including A-element and at least one selected from B-element and C-element, the A-element is at least one selected from Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B-element is at least one selected from Ga, Ti, Zr, and Hf, the C-element is at least one selected from Group 2 elements in periodic table, etching solution A is used when at least one selected from the source electrode and the drain electrode, the gate electrode, and the active layer is formed, and etching solution B that is etching solution having same type as the etching solution A is used when the gate insulating layer is etched.