The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Mar. 29, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Karlo Tskitishvili, Santa Clara, CA (US);

Jeffrey J. Loescher, Portland, OR (US);

Luis D. Guilin, Livermore, CA (US);

Paul M. Furnanz, Lake Oswego, OR (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01);
Abstract

Systems and techniques are described for transparent hierarchical routing in an integrated circuit (IC) design. A logical netlist can be analyzed in the IC design to identify endpoints of a physical route that crosses at least one physical hierarchy boundary. Next, a set of routing shapes can be created to electrically connect the endpoints of the physical route. The set of routing shapes can then be transformed to corresponding routing shapes in each physical hierarchy context along the physical route.


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