The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2020
Filed:
Apr. 26, 2019
Intel Corporation, Santa Clara, CA (US);
Chih-Cheh Chen, Ladera Ranch, CA (US);
Janusz P. Jurski, Beaverton, OR (US);
Amit Kumar Srivastava, Folsom, CA (US);
Malay Trivedi, Chandler, AZ (US);
James Mitchell, Chandler, AZ (US);
Piotr Michael Kwidzinski, Folsom, CA (US);
David N. Lombard, Los Rossmoor, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.