The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2020

Filed:

Nov. 14, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rupin H. Vakharwala, Hillsboro, OR (US);

Camron B. Rust, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 12/1027 (2016.01); G06F 12/1081 (2016.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 9/4401 (2013.01); G06F 12/1027 (2013.01); G06F 12/1081 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/15 (2013.01); G06F 2212/502 (2013.01); G06F 2212/651 (2013.01);
Abstract

Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.


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