High speed voltage level translator including an automatically bootstrapped cascode driver

Abstract

A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.