The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Feb. 19, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Haian Lin, Bethlehem, PA (US);

Frank Alexander Baiocchi, Allentown, PA (US);

Masahiko Higashi, Fukushima, JP;

Namiko Hagane, Fukushima, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/74 (2006.01); H01L 29/76 (2006.01); H03K 17/14 (2006.01); H01L 25/16 (2006.01); H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
H03K 17/145 (2013.01); H01L 21/8249 (2013.01); H01L 25/16 (2013.01); H01L 27/0623 (2013.01); H01L 27/0629 (2013.01);
Abstract

A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.


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