The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Sep. 14, 2017
Applicant:

Sandisk Information Technology (Shanghai) Co., Ltd., Shanghai, CN;

Inventors:

Chin Tien Chiu, Taichung, TW;

Hem Takiar, Fremont, CA (US);

Gursharan Singh, Fremont, CA (US);

Fisher Yu, Shanghai, CN;

C C Liao, Changhua, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3185 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/50 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/37001 (2013.01);
Abstract

The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.


Find Patent Forward Citations

Loading…