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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10811305 B1

PDFFull Text
Date of Patent:
Oct. 20, 2020

Filed:

Sep. 22, 2016

Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Li-Wen Hung, Mahopac, NY (US);

John U. Knickerbocker, Monroe, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Cornelia Tsang Yang, Medford, MA (US);

Bucknell C. Webb, Ossining, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Fleit Intellectual Property Law

Donna Flores

Primary Examiner:

Stephen W Smoot

Assistant Examiner:

Vicki B Booker

Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 21/86 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 27/12 (2006.01); H01L 23/29 (2006.01); H01L 23/00 (2006.01); H01L 21/18 (2006.01); H01L 27/092 (2006.01); H01L 27/06 (2006.01); H01L 21/8258 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76251 (2013.01); H01L 21/187 (2013.01); H01L 21/84 (2013.01); H01L 21/86 (2013.01); H01L 23/291 (2013.01); H01L 23/562 (2013.01); H01L 27/1203 (2013.01); H01L 29/16 (2013.01); H01L 29/1602 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 21/8258 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/8109 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81201 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83047 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/83193 (2013.01); H01L 2224/83896 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2924/0549 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

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