The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2020
Filed:
Feb. 26, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/762 (2006.01); H01L 29/04 (2006.01); H01L 21/67 (2006.01); H01L 29/66 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02669 (2013.01); H01L 21/02104 (2013.01); H01L 21/02532 (2013.01); H01L 21/02667 (2013.01); H01L 21/02672 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/67288 (2013.01); H01L 21/76224 (2013.01); H01L 21/76262 (2013.01); H01L 21/76278 (2013.01); H01L 21/76281 (2013.01); H01L 21/76283 (2013.01); H01L 22/12 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/66651 (2013.01);
Abstract
Methods of forming semiconductor devices are provided. One of the methods includes following steps. A plurality of hard mask patterns is formed around a region of a substrate, wherein an imaginary connecting line is formed between corners of two of the plurality of hard mask patterns at the same side of the region, and the imaginary connecting line is substantially parallel to or perpendicular to a horizontal direction. A semiconductor layer is formed on the substrate by a selective epitaxial growth process.