The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Nov. 07, 2017
Applicant:
Intel Ip Corporation, Santa Clara, CA (US);
Inventors:
Thomas Mayer, Linz, AT;
Christian Wicpalek, Puchenau, AT;
Assignee:
Intel IP Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/04 (2006.01); H03K 3/00 (2006.01); H03L 7/08 (2006.01); G04F 10/00 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 7/58 (2006.01); H03K 3/84 (2006.01); H03L 7/091 (2006.01); H03L 7/099 (2006.01); G06F 1/04 (2006.01); H03L 7/085 (2006.01); H03L 7/197 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); G04F 10/005 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 7/588 (2013.01); H03K 3/84 (2013.01); H03L 7/085 (2013.01); H03L 7/091 (2013.01); H03L 7/0992 (2013.01); H03L 7/197 (2013.01);
Abstract
Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator () configured to output provide a clock signal having a predefined average clock rate, a reference signal generator () configured to provide a reference signal, and a clock divider () configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.