The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Oct. 16, 2019
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Sylvain Engels, Meylan, FR;

Alain Aurand, La Chapelle du Bard, FR;

Etienne Maurin, Seyssins, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/356 (2006.01); H01L 27/02 (2006.01); H03K 3/3562 (2006.01); H03K 19/0948 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356113 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H03K 3/3562 (2013.01); H03K 19/0948 (2013.01);
Abstract

A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).


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