The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Jan. 07, 2020
Applicant:
Semiconductor Components Industries, Llc, Phoenix, AZ (US);
Inventors:
Jie Chang, Suzhou, CN;
Huibin Chen, Suzhou, CN;
Tiburcio Maldo, Consolacion, PH;
Keunhyuk Lee, Suzhou, CN;
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/58 (2011.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01R 13/03 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
H01R 12/585 (2013.01); H01L 23/49517 (2013.01); H01L 23/49541 (2013.01); H01L 23/49555 (2013.01); H01L 23/49579 (2013.01); H01L 23/49811 (2013.01); H01R 13/03 (2013.01); H05K 3/308 (2013.01); H05K 2201/1059 (2013.01);
Abstract
Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.