The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

May. 17, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Jefferson W. Hall, Chandler, AZ (US);

Gordon M. Grivna, Mesa, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76224 (2013.01); H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 21/76895 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 29/0649 (2013.01); H01L 29/407 (2013.01); H01L 29/66712 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01);
Abstract

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.


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