The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Nov. 02, 2011
Viren Khandekar, Flower Mound, TX (US);
Karthik Thambidurai, Plano, TX (US);
Vivek Swaminathan Sridharan, Addison, TX (US);
Viren Khandekar, Flower Mound, TX (US);
Karthik Thambidurai, Plano, TX (US);
Vivek Swaminathan Sridharan, Addison, TX (US);
MAXIM INTEGRATED PRODUCTS, INC., San Jose, CA (US);
Abstract
Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.