The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jul. 07, 2015
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Andrew R. Wilmot, Carlisle, MA (US);

Neeti Khullar Bhatnagar, San Jose, CA (US);

Qizhang Chao, Palo Alto, CA (US);

George Franklin Frazier, Lawrence, KS (US);

Yevgen Ryazanov, San Jose, CA (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 11/30 (2006.01); G06F 117/08 (2020.01);
U.S. Cl.
CPC ...
G06F 9/455 (2013.01); G06F 11/302 (2013.01); G06F 2117/08 (2020.01);
Abstract

According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.


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