The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Jul. 06, 2018
Synopsys, Inc., Mountain View, CA (US);
Andrew Chung Chun Lam, Vaughan, CA;
Davit Petrosyan, Oakville, CA;
Dino A. Toffolon, Stoney Creek, CA;
Morten Christiansen, Sunnyvale, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.