The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Aug. 15, 2019
Applicant:
Ovonyx Memory Technology, Llc, Alexandria, VA (US);
Inventors:
Jun Liu, Boise, ID (US);
Michael P. Violette, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 27/2472 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); G11C 2213/72 (2013.01); G11C 2213/74 (2013.01); G11C 2213/76 (2013.01); G11C 2213/78 (2013.01); G11C 2213/79 (2013.01);
Abstract
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.