The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jan. 29, 2018
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Bin Liu, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Yinjie Ding, Singapore, SG;

Kangho Lee, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 29/78 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); H01L 27/228 (2013.01); H01L 29/785 (2013.01); H01L 43/12 (2013.01);
Abstract

Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.


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