The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Aug. 20, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Smic New Technology Research and Development (Shanghai) Corporation, Shanghai, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/306 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01); H01L 21/822 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/8221 (2013.01); H01L 21/823878 (2013.01); H01L 21/84 (2013.01); H01L 27/0688 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78603 (2013.01); H01L 29/78696 (2013.01); H01L 29/165 (2013.01);
Abstract

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a fin material layer on the semiconductor substrate; forming an isolation material layer having a bandgap greater than a bandgap of the fin material layer on the fin material layer; and forming a stacked channel material layer on the isolation material layer. The stacked channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer. The method also includes etching the stacked channel material layer, the isolation material layer and the fin material layer to form fins protruding from the semiconductor substrate, an isolation layer on the fins and a stacked channel layer on the isolation layer. The stacked channel layer includes a sacrificial layer and a channel layer on the sacrificial material layer.


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Zhou, Fei. (2020). Semiconductor structure and fabrication method thereof (U.S. Patent No. 10797147). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10797147

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