The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Dec. 25, 2018
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Hsueh-Wei Chen, Hsinchu County, TW;

Wei-Ren Chen, Hsinchu County, TW;

Wein-Town Sun, Hsinchu County, TW;

Jui-Ming Kuo, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 27/11558 (2017.01); H01L 27/11524 (2017.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 16/26 (2006.01); H01L 29/788 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/10 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11558 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 29/0649 (2013.01); H01L 29/42328 (2013.01); H01L 29/7885 (2013.01); G11C 16/0483 (2013.01); G11C 2216/04 (2013.01); G11C 2216/10 (2013.01);
Abstract

A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.


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