The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jan. 22, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin-A Kim, Hwaseong-si, KR;

Yong-Kwan Kim, Yongin-si, KR;

Se-Keun Park, Suwon-si, KR;

Joo-Young Lee, Hwaseong-si, KR;

Cha-Won Koh, Yongin-si, KR;

Yeong-Cheol Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 21/28525 (2013.01); H01L 21/3065 (2013.01); H01L 21/76879 (2013.01);
Abstract

A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.


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