The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
May. 25, 2018
Synopsys, Inc., Mountain View, CA (US);
Nabil Yazdani, Nepean, CA;
Donald Oriordan, Mountain View, CA (US);
Jingyu Xu, Beijing, CN;
Bulent Basaran, Atlanta, GA (US);
Larissa Nitchougovskaia, Markham, CA;
SYNOPSYS, INC., Mountain View, CA (US);
Abstract
The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool. Various embodiments include at least a computer-implemented method of performing Voltage-based Design Rule Checking (VDRC) in a full-custom EDA Design and Implementation Platform is provided, the method comprising receiving a plurality of net voltages from at least a first net and a second net, wherein reception of the plurality of net voltages is from one or more of a simulation, a plurality of simulations, manual override, or direct input, determining a net voltage range, the net voltage range being a difference between a first net voltage of a first net and a second net voltage of a second net, causing transfer of the net voltage range to a layout editing process, the layout editing process resulting in generating a layout, and performing VDRC verification, confirming a VDRC clean layout. This Abstract is not intended to limit the scope of the claims.