The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Mar. 06, 2019
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ke-Ying Su, Taipei, TW;
Ke-Wei Su, Zhubei, TW;
Keng-Hua Kuo, Hsinchu, TW;
Lester Chang, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.