The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jan. 22, 2019
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Sanjay Pillay, Aust, TX (US);

Arum Kumar Gogineni, Cedar Park, TX (US);

Srikanth Rengarajan, Austin, TX (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/30 (2020.01); G06F 30/3323 (2020.01);
Abstract

This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.


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