The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Feb. 25, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Venkatraman Iyer, Austin, TX (US);

Darren Jue, Sunnyvale, CA (US);

Sitaraman Iyer, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06N 20/00 (2019.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4004 (2013.01); G06F 13/4221 (2013.01); G06N 20/00 (2019.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.


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