The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Sep. 10, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshiro Riho, Koganei, JP;

Atsushi Shimizu, Hachioji, JP;

Sang-Kyun Park, Boise, ID (US);

Jongtae Kwak, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); H03M 13/00 (2006.01); G11C 29/04 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G06F 11/1044 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); H03M 13/616 (2013.01); G06F 13/4234 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.


Find Patent Forward Citations

Loading…