The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Mar. 24, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bill Nale, Livermore, CA (US);

Jonathan C. Jasper, San Jose, CA (US);

Murugasamy K. Nachimuthu, Beaverton, OR (US);

Jun Zhu, Mountain View, CA (US);

Tuan M. Quach, Fullerton, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/07 (2006.01); G11C 29/02 (2006.01); G06F 12/0813 (2016.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/02 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01); G11C 5/14 (2006.01); H04L 9/08 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 11/079 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 12/023 (2013.01); G06F 12/0802 (2013.01); G06F 12/0813 (2013.01); G06F 13/1663 (2013.01); G06F 13/1678 (2013.01); G06F 13/1689 (2013.01); G06F 13/1694 (2013.01); G06F 13/4234 (2013.01); G06F 13/4243 (2013.01); G06F 13/4282 (2013.01); G11C 5/148 (2013.01); G11C 7/1003 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/40618 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H04L 9/0869 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/60 (2013.01); G11C 5/04 (2013.01); G11C 7/1063 (2013.01);
Abstract

Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.


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