The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jul. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ahmad Yasin, Haifa, IL;

Eti Pardo-Fridman, Haifa, IL;

Ofer Levy, Atlit, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 11/30 (2006.01); G06F 12/08 (2016.01); G06F 1/324 (2019.01); G06F 11/34 (2006.01); G06F 9/30 (2018.01); G06F 12/0897 (2016.01); G06F 12/1027 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3867 (2013.01); G06F 1/324 (2013.01); G06F 9/3016 (2013.01); G06F 9/381 (2013.01); G06F 11/3024 (2013.01); G06F 11/3089 (2013.01); G06F 11/3409 (2013.01); G06F 11/3471 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/452 (2013.01); Y02D 10/126 (2018.01);
Abstract

A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.


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