The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Mar. 08, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Zhao Hui Tang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/02282 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/31111 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/1037 (2013.01); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01);
Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers is formed above a substrate. A dummy channel structure extending vertically through the dielectric stack is formed. An elevating dielectric layer is formed on a dummy dielectric layer. A slit opening extending vertically through the elevating dielectric layer, dummy dielectric layer, and dielectric stack is formed. A memory stack including interleaved conductor layers and the dielectric layers is formed above the substrate by gate replacement. A source contact is formed in the slit opening by depositing a source conductor layer on the elevating dielectric layer and in the slit opening. The source conductor layer on the elevating dielectric layer and at least a part of the elevating dielectric layer are removed.


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