The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Aug. 16, 2019
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Francesco La Rosa, Rousset, FR;

Stephan Niel, Meylan, FR;

Arnaud Regnier, Les Taillades, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11563 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01); H01L 27/11536 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11563 (2013.01); G11C 16/0433 (2013.01); G11C 16/0466 (2013.01); H01L 27/1157 (2013.01); H01L 27/11536 (2013.01); H01L 29/40117 (2019.08); H01L 29/42352 (2013.01);
Abstract

A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.


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