Apparatuses including 3d memory arrays, methods of forming the apparatuses, and related electronic systems

Abstract

An apparatus comprises a base structure, a memory structure, and interconnect structures. The base structure comprises odd sense amplifiers and even sense amplifiers. The memory structure comprises 3D memory arrays having decks each comprising digit lines, additional digit lines, memory cells, and word lines. The digit lines comprise odd digit lines and even digit lines, and the additional digit lines comprise additional odd digit lines and additional even digit lines. The memory cells are connected to the digit lines and the additional digit lines, and each comprise two transistors and one capacitor. The word lines are connected to the memory cells, and comprise odd word lines and even word lines. The interconnect structures comprise odd interconnect structures connecting the odd sense amplifiers to the odd digit lines and the additional odd digit lines, and even interconnect structures connecting the even sense amplifiers to the even digit lines and the additional even digit lines. Related electronic systems and methods are also described.