The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jun. 05, 2019
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Piyush Sagdeo, San Jose, CA (US);

Chris Yip, San Jose, CA (US);

Sourabh Sankule, San Jose, CA (US);

Pitamber Shukla, San Jose, CA (US);

Anubhav Khandelwal, San Jose, CA (US);

Mohan Dunga, San Jose, CA (US);

Niles Yang, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 29/50 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3418 (2013.01); G06F 11/076 (2013.01); G06F 11/0793 (2013.01); G11C 16/34 (2013.01); G11C 16/3422 (2013.01); G11C 29/50012 (2013.01); G11C 2029/5004 (2013.01); G11C 2211/563 (2013.01);
Abstract

A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.


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