The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Mar. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mohan K. Nair, Portland, OR (US);

Rajesh M. Sankaran, Portland, OR (US);

Utkarsh Y. Kakaiya, Folsom, CA (US);

Zhenfu Chai, Shanghai, CN;

David M. Lee, Portland, OR (US);

Pratik M. Marolia, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/4401 (2018.01); G06F 21/60 (2013.01); G06F 21/85 (2013.01); G06F 21/57 (2013.01); G06F 12/0815 (2016.01); G06F 13/42 (2006.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/602 (2013.01); G06F 9/4403 (2013.01); G06F 12/0815 (2013.01); G06F 21/575 (2013.01); G06F 21/85 (2013.01); G06F 9/4406 (2013.01); G06F 9/4408 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1052 (2013.01); G06F 2213/0026 (2013.01); H04L 63/04 (2013.01);
Abstract

In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.


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