The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Aug. 09, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ren Wang, Portland, OR (US);

Yipeng Wang, Hillsboro, OR (US);

Tsung-Yuan Tai, Portland, OR (US);

Cristian Florin Dumitrescu, Shannon, IE;

Xiangyang Guo, Bellevue, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/123 (2016.01); G06F 12/126 (2016.01); G06F 12/128 (2016.01); G06F 12/0864 (2016.01); G06F 12/0891 (2016.01); G06F 9/30 (2018.01); G06F 12/0871 (2016.01);
U.S. Cl.
CPC ...
G06F 12/123 (2013.01); G06F 9/30036 (2013.01); G06F 12/0864 (2013.01); G06F 12/0871 (2013.01); G06F 12/0891 (2013.01); G06F 12/126 (2013.01); G06F 12/128 (2013.01);
Abstract

Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device retrieves a bucket of an associative cache from memory that includes multiple entries arranged from front to back. The bucket may be a 256-bit array including eight 32-bit entries. For lookups, a matching entry is located at a position in the bucket. The computing device executes a vector permutation processor instruction that moves the matching entry to the front of the bucket while preserving the order of other entries of the bucket. For insertion, an inserted entry is written at the back of the bucket. The computing device executes a vector permutation processor instruction that moves the inserted entry to the front of the bucket while preserving the order of other entries. The permuted bucket is stored to the memory. Other embodiments are described and claimed.


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