The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Feb. 21, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Yizhong Zhang, Suzhou, CN;

Stefano Pietri, Austin, TX (US);

James Robert Feddeler, Lake Village, IN (US);

Michael Todd Berens, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/68 (2006.01); H03M 1/76 (2006.01); H03M 1/78 (2006.01); H03M 1/80 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/687 (2013.01); H03M 1/765 (2013.01); H03M 1/785 (2013.01); H03M 1/00 (2013.01); H03M 1/66 (2013.01); H03M 1/80 (2013.01);
Abstract

A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.


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