The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
May. 15, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Pascal Meinerzhagen, Hillsboro, OR (US);
Vivek De, Beaverton, OR (US);
Muhammad Khellah, Tigard, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 5/14 (2014.01); G06F 1/10 (2006.01); H03K 5/135 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00323 (2013.01); G06F 1/10 (2013.01); H03K 5/135 (2013.01); H03K 5/14 (2013.01);
Abstract
A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.