The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Nov. 17, 2018
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Fandong Liu, Wuhan, CN;

Wenyu Hua, Wuhan, CN;

Jia He, Wuhan, CN;

Linchen Wu, Wuhan, CN;

Yue Qiang Pu, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/11556 (2017.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/31111 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 27/11556 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02183 (2013.01); H01L 21/02186 (2013.01); H01L 21/02189 (2013.01);
Abstract

Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.


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