The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Nov. 27, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Wei-Lun Hsu, Hsinchu County, TW;

Yung-Chien Kung, Tainan, TW;

Ming-Tsung Yeh, Taipei, TW;

Yan-Hsiu Liu, Tainan, TW;

Am-Tay Luy, Zhubei, TW;

Yao-Pi Hsu, Zhubei, TW;

Ji-Fu Kung, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/146 (2006.01); H01L 27/092 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 21/761 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01); H01L 21/823878 (2013.01); H01L 21/823481 (2013.01); H01L 21/823892 (2013.01); H01L 29/7813 (2013.01);
Abstract

An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.


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