The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
Sep. 20, 2018
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Shao-Chang Huang, Hsinchu, TW;
Li-Fan Chen, Hsinchu, TW;
Chih-Hsuan Lin, Hsinchu, TW;
Yu-Kai Wang, Hsinchu, TW;
Hung-Wei Chen, Jhubei, TW;
Ching-Wen Wang, Hemei Township, TW;
Ting-You Lin, Hsinchu, TW;
Chun-Chih Chen, New Taipei, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.